1.0 Phase Lock Loop (PLL) Theory of Operation
FIG. 1 provides an illustration of a Phase-Lock-Loop (PLL) 100. As seen in FIG. 1, a typical PLL includes a phase detector 101, a charge pump 102, a loop filter 103, a Voltage Controlled Oscillator (VCO) 104 and a feedback divider 105. PLLs are often used for frequency multiplication, wherein, the frequency of an input reference signal 106 is effectively multiplied. That is, the output signal 107 frequency of the PLL 100 (which corresponds to the output signal 107 frequency of the VCO 104) will be a multiple of the frequency of the input reference signal 106. According to basic principles of PLL operation, the multiplication is coextensive with the frequency division “M” performed by feedback divider 105.
Better said, if the feedback divider 105 reduces the frequency of the VCO output signal 107 by a factor of M, the frequency of the VCO output signal 107 should be a factor M of the reference signal 106 frequency. A working PLL 100 may be thought of as a stable control system that is designed to “automatically” drive an error term magnitude to zero. Here, the error term magnitude can be thought of as effectively representing the difference between the actual VCO output signal 107 frequency and the correct VCO output signal 107 frequency. In reality, the error term magnitude represents the difference between the actual VCO output signal 107 phase and the correct VCO output signal 107 phase. The correct VCO output signal 107 frequency, as discussed above, corresponds to MfREF where M is the frequency division performed by the feedback divider 105 and fREF is the input reference signal 106 frequency.
Thus, when the VCO output signal 107 frequency deviates from MfREF, a non zero error term magnitude is created that causes the VCO output signal 107 frequency to change in a direction that corrects for the error. Notice that the error term may also be described as having a polarity (e.g., positive or negative) so that the appropriate direction of VCO output signal 107 frequency change is represented. For example, if the VCO output signal 107 frequency is less than MfREF (i.e., the VCO output signal 107 frequency is too low), a positive error term is created that causes the VCO output signal 107 frequency to increase. Likewise, if the VCO output signal 107 frequency is greater than MfREF (i.e., the VCO output signal 107 frequency is too high), a negative error term is created that causes the VCO output signal 107 frequency to decrease.
The polarity of the error term is a matter of definition and may be “flipped” from that described just above depending on the particular definitional preference of the designer (i.e., some designs may choose to define a negative error term as corresponding to a situation where the VCO output signal is too low and a positive error term as corresponding to a situation where the VCO output signal is too high). For convenience, the terminology initially described above (wherein a positive error term causes a VCO output signal 107 frequency increase and a negative error term causes a VCO output signal 107 frequency decrease) will be used throughout the present application.
Referring to the PLL topology 100 of FIG. 1, the error term is presented at the output of the phase detector 101. As such, in order to effectively compare the “actual” VCO output signal 107 frequency against the “correct” VCO output signal 107 frequency (so that an appropriate error term may be crafted), notice that the phase detector 101 receives both the input reference signal 106 and the output signal 108 of the feedback divider 105. With a correct VCO output signal frequency corresponding to MfREF; and, with the feedback divider 105 dividing down the frequency of the VCO output signal 107 by a factor of M; note that, when the frequency of the VCO output signal 107 is correct (i.e., is equal to MfREF), the frequency of the input reference signal 106 (i.e., fREF) and the frequency of the frequency divider output signal 108 should be the same (i.e., the frequency of the feedback divider output signal 108 should also be fREF).
Likewise, deviations of the VCO output signal 107 frequency away from its correct value (MfREF) would cause the frequency of the feedback divider output signal 108 to correspondingly deviate from a frequency of fREF. As such, the phase detector 101 effectively uses the input reference signal 106 frequency as a “benchmark” against which the frequency of the feedback divider output signal 108 is compared. The comparison results in an error term being crafted having both magnitude information (which expresses the extent to which the pair of frequencies are dissimilar) and polarity information (which expresses which signal has greater frequency). When the frequencies are the same, the error term should have a magnitude of zero (meaning no change in VCO output signal 108 frequency is needed); and, when the frequencies are different, the error term should have a magnitude that is representative of the amount of difference as well as a polarity that indicates whether or not the feedback divider output signal 108 frequency is less than or greater than fREF.
The phase detector 101 is typically designed to effectively compare the frequencies of its input signals 106, 108 in the time domain rather than the frequency domain; and, as such, compares the phase positioning of signals 106, 108 (hence the name “phase” detector). Here, as depicted at the inset 109 of FIG. 1, if the phase detector 101 observes that an edge of the feedback divider output signal 108 is “lagging” an edge of the input reference signal 106, the phase detector will craft a positive error term (indicating that the VCO output signal 107 frequency is too low); and, likewise, as observed at inset 110, if the phase detector 101 observes that an edge of the feedback divider output signal 108 is “leading” 111 an edge of the input reference signal 106, the phase detector will craft a negative error term (indicating the VCO output signal 107 frequency is too high).
In either case, the magnitude of the error term will indicate the extent to which the edges being compared are misaligned in time. If the VCO output signal frequency and phase are “correct”, the edges should be aligned in time (as indicated at inset 111) which corresponds to an error term having zero magnitude. Note that the particular phase detector 101 embodiment of FIG. 1 uses different outputs to indicate error term polarity. That is, if the error term polarity is positive (so as to cause an increase in VCO output signal 107 frequency), a pulse will appear at a first output 112 (“up”); and, if the error term polarity is negative (so as to cause a decrease in VCO output signal 107 frequency), a pulse will appear at a second output 113 (“down”). In either case, the width of the pulse in time reflects the magnitude of the error term.
The PLL 100 is configured such that, after an initial period of time, the PLL will automatically acquire “phase lock” as depicted in depiction 111. This effectively corresponds to the PLL automatically driving the error term magnitude to zero (which also corresponds in kind to the VCO output signal 107 frequency being driven to a value of MfREF) over this same initial time persiod. The error term magnitude is automatically driven to zero because of the activity of the charge pump 102, loop filter 103 and VCO 104. A VCO 104 is a circuit that produces, at its output, a signal 107 whose frequency is a function of the voltage placed at its input 114. The charge pump 102 and loop filter 103 effectively cause a change in the voltage level of VCO input 114, where the voltage change is related to the error term information. That is, the size of the voltage change (e.g., in volts) is related to the magnitude of the error term and the direction of the voltage change (e.g., up or down) is related to the polarity of the error term.
As the loop filter 103 is comprised of a capacitor that is shunted to ground, the voltage level of the VCO input 114 can be increased by pumping charge into the loop filter 103; and, the voltage level of the VCO input 114 can be decreased by extracting charge from the loop filter 103. The charge pump 102 serves this function as it is configured to: 1) pump charge into the loop filter 103 so as to raise the VCO input 114 voltage (e.g., in response to a positive error term); and, 2) extract charge from the loop filter 103 so as to lower the VCO input 114 voltage (e.g., in response to a negative error term). The amount of charge pumped into or extracted from the loop filter 103 is proportional to the magnitude of the error term (so that the voltage change is proportional to the magnitude of the error term).
The loop filter 103 “holds” the voltage level of the VCO input 114 to that which the charge pump 102 changed it to. Here, a voltage change that causes the VCO output signal 107 frequency to be more accurate (i.e., closer to MfREF) should cause a subsequent error term to have less magnitude; while, a voltage change that causes the VCO output signal 107 frequency to be less accurate (i.e., farther from MfREF) should cause a subsequent error term to have greater magnitude. Thus, the more accurate the VCO output signal 107 frequency becomes, the less the voltage level at the VCO input 114 will be changed. This activity causes the PLL 100 to naturally guide its VCO input 114 voltage level to a voltage that corresponds to the correct VCO output signal 107 frequency. This, in turn, corresponds to the error magnitude term being automatically driven to zero.
2.0 Phase Lock Loop Characteristics
The previous discussion provided an overview of a theory of operation for a PLL. PLLs are typically constructed with electronic circuit components (e.g., transistors, capacitors, resistors, etc.) that have limited performance and/or performance characteristics that may vary as a function of manufacturing tolerances and/or environmental conditions. As such, when actually implemented in hardware, a PLL may stray from its perfect theoretical operation or otherwise possess imperfections that can affect other circuitry that depends on the operation of the PLL. Furthermore, the dynamics of “loop stability” (i.e., wherein an error term magnitude is automatically driven to zero) are more complicated than that described in the preceding section to the extent some additional “conditions” apply to the PLL's basic building blocks 101, 102, 103, 104, 105. As such, various performance characteristics are understood to exist for PLLs that help describe the imperfections and/or help identify whether or not the PLL will be stable over the region of desired operation. Some of these include (among possible others): 1) static phase error; 2) stability; and 3) jitter. A discussion of each of these is provided immediately below.
2.1 Static Phase Error
From the discussion of Section 1.0 (and in particular to the discussion of phase lock described with respect to inset 112 of FIG. 1), recall that a PLL should normally adjust the VCO output signal 107 frequency until the edges of the reference input signal 106 and the feedback divider output signal 108 are aligned with one another. By contrast, FIG. 2A shows a depiction of the static phase error that may exist within a PLL. From the depiction of FIG. 2A it is evident that static phase error corresponds to the tendency of a PLL to lock onto a mis-aligned relationship between the reference input signal 206 and the feedback divider output signal 208.
Typically, when a PLL exhibits static phase error, it is because of imperfections in the phase detector 101 and charge pump 102 that “effectively” cause a mis-aligned reference input signal 206/feedback divider output signal 208 condition (e.g., as depicted in FIG. 2A) to produce an error term having zero magnitude (i.e., no error term) from the perspective of the VCO input 114. Likewise, a properly aligned reference input signal/feedback divider output signal condition (e.g., as depicted at inset 111 of FIG. 1), “effectively” causes an error term having non zero magnitude from the perspective of the VCO input 114. This, in turn, corresponds to the VCO output signal 107 phase being misaligned from the phase of the correct value (Mfref), even though the VCO output signal 107 frequency is the correct value (Mfref).
2.2 Stability
Stability is a term of art used to refer to a pair of characteristics that can be used to describe whether or not a PLL will automatically drive the error term magnitude to zero (so as to produce the correct VCO output signal frequency). In general, the stability of a PLL depends upon whether or not it is behaving as a negative feedback loop. The PLL theory of operation provided in Section 1.0 effectively described negative feedback because (as described in Section 1.0): 1) if the frequency of the VCO output signal 107 was greater than its “correct” value of MfREF, the PLL acted to reduce the VCO output signal 107 frequency; and 2) if the frequency of the VCO output signal 107 was less than its “correct” value of MfREF, the PLL acted to increase the VCO output signal 107 frequency.
If the PLL were to operate inapposite to that described just above (i.e., if the VCO output signal frequency was increased in response to the phase detector's determining that the VCO output signal was above its correct output frequency; and/or, if the VCO output signal frequency was decreased in response to the phase detector's determining that the VCO output signal was beneath its correct output frequency), the PLL would be unstable because the VCO output signal frequency would tend to continually rise or tend to continually fall. Typically, the PLL parameters of “cross-over-frequency” and “phase margin” are used to help understand whether the PLL is operating within the realm of negative feedback.
A depiction of the cross over frequency 210 and phase margin 211 are shown in FIG. 2B. The cross over frequency is the frequency at which the transfer function 212 of the PLL reaches unity. Here, as the loop filter 103 is a low pass filter, the PLL channel (which can be viewed as the signal processing that occurs through one pass through the loop of the PLL) has a response that varies with frequency as depicted in transfer function 212. The phase margin 211 of the PLL is the difference between the phase delay through the PLL channel and 180 degrees at the cross over frequency 210. An example of the difference between the phase delay and 180 degrees of the PLL channel is observed in curve 213 of FIG. 2B. Here, the more the phase margin rises above −180 degrees, the more the PLL is operating within a negative feedback (and therefore stable) region of operation.
2.3 Jitter
Jitter relates to the variation in the period of the VCO output signal 107 with respect to an ideal output signal, Mfref, once phase lock has been acquired. Because of systematic variations at the VCO input 114, as shown in FIG. 2C, as well as random variations (due to thermal noise, for example), the instantaneous frequency at the VCO output signal 107 will not always be equal to Mfref, even though the average VCO output signal 107 frequency is correct. This will cause the time at which the rising edge of the VCO output signal 107 occurs to vary with respect to where the rising edge of Mfref would ideally occur. The maximum variation of the rising edges is undesirable, and is called jitter.
3.0 Lack of Widely Accepted Automated Analog and/or Mixed Signal Design Technology
Digital signal processing “reacts” to an input signal depending on whether the input signal is recognized as a “1” or a “0”. Likewise, digital signal processing generates an output signal from the perspective that the output signal corresponds to a “1” or a “0”. Analog signal processing, by contrast, views an input signal as being continuous (rather than discrete “1”s or “0”s); and, on the output side, tailors a continuous output signal (as opposed to discrete “1”s or “0”s). When both analog and digital signal processing techniques are significantly involved in the overall function of an electronic circuit, the electronic circuit may be referred to as a “mixed signal” circuit.
That is, mixed signal refers to the notion that both digital signal processing and analog signal processing are being performed with the same circuit. As such, mixed signal circuitry and analog circuitry are both configured to process analog signals (and, likewise, contain some degree of analog circuitry). Here, PLLs are often characterized as mixed signal or analog. The charge pump 102, loop filter 103 and VCO 104 are regarded as analog building blocks while the feedback divider 105 and phase detector 101 are regarded as being either digital or analog building blocks. Unfortunately, the design of analog and (at least the analog portion of) mixed signal circuit design has traditionally involved manual, hand crafted techniques rather than automated techniques. Here, the manual, hand crafted approach to analog and mixed signal circuit design tends to slow down or otherwise complicate the circuit design flow process.
With semiconductor minimum feature sizes approaching 0.10 micron and below, highly integrated semiconductor chips are expected that will integrate significant amounts of both digital signal processing circuitry and analog signal processing circuitry onto the same semiconductor chip. Furthermore, with the growth of networking and handheld applications, analog signal processing has observed a surge in interest (because communication and handheld circuits tend to depend more upon analog/mixed signal functionality than those used for desktop or raised floor computing system applications).
As such, analog and mixed signal circuit design techniques have received widespread attention recently because of the relative scarcity of analog circuit designers (in light of the increased demand for analog and mixed signal circuit designs themselves) combined with the manual, hand crafted approach to analog and mixed signal circuit design. Better said, the combination of manual design techniques, a small supply of analog designers and the increased demand for analog and mixed signal circuit designs has threatened the ability of analog/mixed signal circuit design teams to meet demand in a timely fashion. PLLs, being regarded as one of the more commonly used analog or mixed signal circuits, therefore tend to complicate or extend the development strategy of the many semiconductor chips because of the manual, hand crafted approach to PLL circuit design.